As a conventionally known method of configuring an accelerator in a computer system, there are a single instruction stream, multiple data stream (SIMD) method of a shared external cache type and an external accelerator method of a shared main storage type.
When a general-purpose central processing unit (CPU) sends data to an accelerator, it is only necessary to write back (flush) internal cache data to an external cache in the case of the shared external cache type. However, since an external cache memory generally has a data width close to an SIMD width, it is not possible to refer, at one time, to a large amount of data that exceeds the SIMD width. On the other hand, in the case of the shared main storage type, it is necessary to write back (flush) both internal cache data and external cache data to a main storage. This causes a cache flush time to become a large overhead.
In view of the above, there has been a proposal on a configuration provided with a buffer memory, which serves as a cache memory for a core and also as a local memory for each accelerator (see Non-Patent Literature 1 (FIG. 1)).
With this configuration, the local memory of each accelerator and the cache memory are one shared buffer memory. This leads to reduction of the above-described overhead.